openocd dap 相关

首先，需要了解 [[ARM Debug Interface v5]] 内容，然后才可以通过以下 [[openocd]] 命令进行 dap 寄存器的读取。

基础命令#

TAP Declaration (OpenOCD User’s Guide)
Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is no longer implicitly created together with the target. It must be explicitly declared using the dap create command. For all ARMv6-M, ARMv7 and ARMv8 targets, the option "-dap dap_name" has to be used instead of "-chain-position dotted.name" when the target is created.

The dap command group supports the following sub-commands:

Command: dap create dap_name -chain-position dotted.name configparams...

Declare a DAP instance named dap_name linked to the JTAG tap dotted.name. This also creates a new command (dap_name) which is used for various purposes including additional configuration. There can only be one DAP for each JTAG tap in the system.

A DAP may also provide optional configparams:

-adiv5 Specify that it’s an ADIv5 DAP. This is the default if not specified.

-adiv6 Specify that it’s an ADIv6 DAP.

-ignore-syspwrupack Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT register during initial examination and when checking the sticky error bit. This bit is normally checked after setting the CSYSPWRUPREQ bit, but some devices do not set the ack bit until sometime later.

-dp-id number
Debug port identification number for SWD DPv2 multidrop. The number is written to bits 0..27 of DP TARGETSEL during DP selection. To find the id number of a single connected device read DP TARGETID: device.dap dpreg 0x24 Use bits 0..27 of TARGETID.

-instance-id number
Instance identification number for SWD DPv2 multidrop. The number is written to bits 28..31 of DP TARGETSEL during DP selection. To find the instance number of a single connected device read DP DLPIDR: device.dap dpreg 0x34 The instance number is in bits 28..31 of DLPIDR value.

Command: dap names

This command returns a list of all registered DAP objects. It it useful mainly for TCL scripting.

Command: dap info [num|root]

Displays the ROM table for MEM-AP num, defaulting to the currently selected AP of the currently selected target. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP. With ADIv6 only, root specifies the root ROM table.

显示 MEM-AP 编号的 ROM 表，默认为当前所选目标的当前所选 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。仅对于 ADIv6，root 指定根 ROM 表。

Command: dap init

Initialize all registered DAPs. This command is used internally during initialization. It can be issued at any time after the initialization, too.

The following commands exist as subcommands of DAP instances:

Command: $dap_name info [num|root]

Displays the ROM table for MEM-AP num, defaulting to the currently selected AP. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP. With ADIv6 only, root specifies the root ROM table.

显示 MEM-AP 编号的 ROM 表，默认为当前选择的 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。仅对于 ADIv6，root 指定根 ROM 表。

Command: $dap_name apid [num]

Displays ID register from AP num, defaulting to the currently selected AP. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP.

显示 AP num 的 ID 寄存器，默认为当前选定的 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。

Command: $dap_name apreg ap_num reg [value]

Displays content of a register reg from AP ap_num or set a new value value. On ADIv5 DAP ap_num is the numeric index of the AP. On ADIv6 DAP ap_num is the base address of the AP. reg is byte address of a word register, 0, 4, 8 ... 0xfc.

显示 AP ap_num 寄存器寄存器的内容或设置新值。在 ADIv5 DAP 中，ap_num 是 AP 的数字索引。在 ADIv6 DAP 中，ap_num 是 AP 的基地址。 reg 是字寄存器的字节地址，0、4、8 ...0xfc。

Command: $dap_name apsel [num]

Select AP num, defaulting to 0. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP.

选择 AP num，默认为 0。在 ADIv5 中，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。

Command: $dap_name dpreg reg [value]

Displays the content of DP register at address reg, or set it to a new value value.

In case of SWD, reg is a value in packed format dpbanksel << 4 | addr and assumes values 0, 4, 8 ... 0xfc. In case of JTAG it only assumes values 0, 4, 8 and 0xc.

Note: Consider using poll off to avoid any disturbing background activity by OpenOCD while you are operating at such low-level.

显示地址为 reg 的 DP 寄存器内容，或将其设置为新值。

如果是 SWD，reg 是一个打包格式为 dpbanksel << 4 | addr 的值，取值范围为 0、4、8 ...0xfc。如果是 JTAG，则只取值 0、4、8 和 0xc。

_Note:_考虑使用 "poll off"（关闭轮询），以避免 OpenOCD 在低级运行时进行任何干扰性的后台活动。

Command: $dap_name baseaddr [num]_

Displays debug base address from MEM-AP num, defaulting to the currently selected AP. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP.

显示 MEM-AP num 的调试基地址，默认为当前选定的 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。

Command: $dap_name memaccess [value]

Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP memory bus access [0-255], giving additional time to respond to reads. If value is defined, first assigns that.

显示 JTAG 空闲时用于 MEM-AP 内存总线访问的额外 tck 周期数 [0-255]，为读取数据提供额外的响应时间。如果已定义值，则首先分配该值。

Command: $dap_name apcsw [value [mask]]

Displays or changes CSW bit pattern for MEM-AP transfers.

显示或更改 MEM-AP 传输的 CSW 位模式。

At the begin of each memory access the CSW pattern is extended (bitwise or-ed) by Size and AddrInc bit-fields according to transfer requirements and the result is written to the real CSW register. All bits except dynamically updated fields Size and AddrInc can be changed by changing the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A for details.

在每次内存访问开始时，CSW 模式会根据传输要求通过 Size 和 AddrInc 位字段进行扩展（按位或编辑），并将结果写入真正的 CSW 寄存器。除了动态更新的 Size 和 AddrInc 字段外，所有位都可以通过更改 CSW 模式来改变。详情请参阅 ARM ADI v5 手册第 7.6.4 章和附录 A。

Use value only syntax if you want to set the new CSW pattern as a whole. The example sets HPROT1 bit (required by Cortex-M) and clears the rest of the pattern:

如果要设置整个新 CSW 模式，请使用仅值语法。示例设置了 HPROT1 位（Cortex-M 要求），并清除了模式的其他部分：

kx.dap apcsw 0x2000000

If mask is also used, the CSW pattern is changed only on bit positions where the mask bit is 1. The following example sets HPROT3 (cacheable) and leaves the rest of the pattern intact. It configures memory access through DCache on Cortex-M7.

如果还使用掩码，则 CSW 模式仅在掩码位为 1 的位位置上更改。以下示例设置 HPROT3（可缓存）并保持模式的其余部分不变。它通过 Cortex-M7 上的 DCache 配置内存访问。

set CSW_HPROT3_CACHEABLE [expr {1 << 27}]
samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE

Another example clears SPROT bit and leaves the rest of pattern intact:

set CSW_SPROT [expr {1 << 30}]
samv.dap apcsw 0 $CSW_SPROT

Note: If you want to check the real value of CSW, not CSW pattern, use xxx.dap apreg 0. See DAP subcommand apreg.

Warning: Some of the CSW bits are vital for working memory transfer. If you set a wrong CSW pattern and MEM-AP stopped working, use the following example with a proper dap name:

xxx.dap apcsw default

读取 DP 寄存器#

以下内容都引用于 [[ARM Debug Interface v5]]
首先，读取 DP 寄存器使用上述命令中的

Command: $dap_name dpreg reg [value]

Displays the content of DP register at address reg, or set it to a new value value.

In case of SWD, reg is a value in packed format dpbanksel << 4 | addr and assumes values 0, 4, 8 ... 0xfc. In case of JTAG it only assumes values 0, 4, 8 and 0xc.

Note: Consider using poll off to avoid any disturbing background activity by OpenOCD while you are operating at such low-level.

显示地址为 reg 的 DP 寄存器内容，或将其设置为新值。

如果是 SWD，reg 是一个打包格式为 dpbanksel << 4 | addr 的值，取值范围为 0、4、8 ...0xfc。如果是 JTAG，则只取值 0、4、8 和 0xc。

_Note:_考虑使用 "poll off"（关闭轮询），以避免 OpenOCD 在低级运行时进行任何干扰性的后台活动。

因此，我们需要确认填入的内容 reg 也就是 dpbanksel << 4 | addr 的值。
Pasted image 20240507162428

由上图可知，dpbanksel 为任意值，addr 为 0，也就是以下命令即可读取出 DPIDR 的值

$dap_name dpreg 0

实际读取：

> rk3568.dap dpreg 0
0x2ba01477

其他 DP 寄存器也读取一下：

> rk3568.dap dpreg 0     #DPIDR
0x2ba01477
> rk3568.dap dpreg 0x4   #CTRL/STAT
0xf0000041
> rk3568.dap dpreg 0x14  #DLCR
0x00000043
> rk3568.dap dpreg 0x24  #TARGETID
0xf0000041
> rk3568.dap dpreg 0x34  #DLPIDR
0x00000043
> rk3568.dap dpreg 0x44  #EVENTSTAT
0xf0000041
> rk3568.dap dpreg 0xc0  #RDBUFF
0x2ba01477
>

读取 AP 寄存器#

首先，读取 AP 寄存器使用上述命令中的

Command: $dap_name apreg ap_num reg [value]

Displays content of a register reg from AP ap_num or set a new value value. On ADIv5 DAP ap_num is the numeric index of the AP. On ADIv6 DAP ap_num is the base address of the AP. reg is byte address of a word register, 0, 4, 8 ... 0xfc.

显示 AP ap_num 寄存器寄存器的内容或设置新值。在 ADIv5 DAP 中，ap_num 是 AP 的数字索引。在 ADIv6 DAP 中，ap_num 是 AP 的基地址。 reg 是字寄存器的字节地址，0、4、8 ...0xfc。

其次需要确认 ap_num 也就是 AP 的数字索引，可以使用

Command: $dap_name apid [num]

Displays ID register from AP num, defaulting to the currently selected AP. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP.

显示 AP num 的 ID 寄存器，默认为当前选定的 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。

> rk3568.dap apid
0x24770002
> rk3568.dap apid 0
0x24770002
> rk3568.dap apid 1
0x00000000

由此确认当前选定的 AP 的数字索引为 0

再次就是确认 reg，寄存器的字节地址
Pasted image 20240507165919

开始读取寄存器的值：

> rk3568.dap apreg 0 0x00  #CSW
0x80000042
> rk3568.dap apreg 0 0x04  
0x81004310
> rk3568.dap apreg 0 0x08  #TAR
0x00000000
> rk3568.dap apreg 0 0x0c  #DRW
0x00000000
> rk3568.dap apreg 0 0x10  #BD0
0x00000000
> rk3568.dap apreg 0 0x14  #BD1
0x00000011
> rk3568.dap apreg 0 0x18  #BD2
0x00000000
> rk3568.dap apreg 0 0x1c  #BD3
0x00000000
> rk3568.dap apreg 0 0x20  #MBT
0x00000000
> rk3568.dap apreg 0 0x30  #T0TR
0x00000000
> rk3568.dap apreg 0 0xe0  #CFG1
0x00000000
> rk3568.dap apreg 0 0xf0  #BASE
0x00000000
> rk3568.dap apreg 0 0xf4  #CFG
0x00000000
> rk3568.dap apreg 0 0xf8  #BASE
0x80000003
> rk3568.dap apreg 0 0xfc  #IDR
0x24770002

读取 ROM Tables#

Command: $dap_name info [num|root]

Displays the ROM table for MEM-AP num, defaulting to the currently selected AP. On ADIv5 DAP num is the numeric index of the AP. On ADIv6 DAP num is the base address of the AP. With ADIv6 only, root specifies the root ROM table.

显示 MEM-AP 编号的 ROM 表，默认为当前选择的 AP。在 ADIv5 上，DAP num 是 AP 的数字索引。在 ADIv6 上，DAP num 是 AP 的基地址。仅对于 ADIv6，root 指定根 ROM 表。

> rk3568.dap info
AP # 0x0
                AP ID register 0x24770002
                Type is MEM-AP APB2 or APB3
MEM-AP BASE 0x80000003
                Valid ROM table present
                Component base address 0x80000000
                Peripheral ID 0x0000080000
                Designer is 0x000, <invalid>
                Part is 0x000, Unrecognized
                Component class is 0x1, ROM table
                MEMTYPE system memory not present: dedicated debug bus
        ROMTABLE[0x0] = 0x01000003
                Component base address 0x81000000
                Peripheral ID 0x04007bb4e3
                Designer is 0x23b, ARM Ltd
                Part is 0x4e3, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x00, Miscellaneous, other
                Dev Arch is 0x47700af7, ARM Ltd "CoreSight ROM architecture" rev.0
                Type is ROM table
                MEMTYPE system memory not present: dedicated debug bus
        [L01] ROMTABLE[0x0] = 0x00001006
                Component not present
        [L01] ROMTABLE[0x4] = 0x00002006
                Component not present
        [L01] ROMTABLE[0x8] = 0x00004003
                Component base address 0x81004000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0xc] = 0x00005003
                Component base address 0x81005000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x10] = 0x00006003
                Component base address 0x81006000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x14] = 0x00007003
                Component base address 0x81007000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x18] = 0x00008002
                Component not present
        [L01] ROMTABLE[0x1c] = 0x00009002
                Component not present
        [L01] ROMTABLE[0x20] = 0x0000a002
                Component not present
        [L01] ROMTABLE[0x24] = 0x0000b002
                Component not present
        [L01] ROMTABLE[0x28] = 0x0000c003
                Component base address 0x8100c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x2c] = 0x0000d003
                Component base address 0x8100d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x30] = 0x0000e003
                Component base address 0x8100e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x34] = 0x0000f003
                Component base address 0x8100f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x38] = 0x00014003
                Component base address 0x81014000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x3c] = 0x00015003
                Component base address 0x81015000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x40] = 0x00016003
                Component base address 0x81016000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x44] = 0x00017003
                Component base address 0x81017000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x48] = 0x0001c003
                Component base address 0x8101c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x4c] = 0x0001d003
                Component base address 0x8101d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x50] = 0x0001e003
                Component base address 0x8101e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x54] = 0x0001f003
                Component base address 0x8101f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x58] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x5c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x60] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x64] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x68] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x6c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x70] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x74] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x78] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x7c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x80] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x84] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x88] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x8c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x90] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x94] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x98] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x9c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xac] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xbc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xcc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xdc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xec] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xfc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x100] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x104] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x108] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x10c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x110] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x114] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x118] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x11c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x120] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x124] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x128] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x12c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x130] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x134] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x138] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x13c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x140] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x144] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x148] = 0x00000000
        [L01]   End of ROM table
        ROMTABLE[0x4] = 0x00000000
                End of ROM table
>