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openocd cti アドレスとデバッグアドレス

#openocd151
AI 翻訳
この記事はAIを通じて英語から日本語に翻訳されました。原文を表示
AI が生成した要約
本篇主要讲解[[openocd]]配置文件中的cti address和debug address的解析和使用。配置文件中包含了对rk3568芯片的配置信息，包括DAP设置、adapter设置、SWD tap设置等。通过设置cti address和debug address，可以创建和访问CTI对象以及调试基地址。配置文件解析过程包括cti create和target create命令的解析，通过调用相应的函数实现配置文件转换为结构体链表。

本篇は、[[openocd]] の設定ファイル内の cti アドレスとデバッグアドレスの解析方法と使用方法について説明します。

設定ファイル#

[!/usr/local/share/openocd/scripts/target/rk3568.cfg]

# SPDX-License-Identifier: GPL-2.0-or-later
reset_config trst_and_srst separate
if { [info exists CHIPNAME] } {
  set _CHIPNAME $CHIPNAME
} else {
  set _CHIPNAME rk3568
}

#
# Main DAP
#
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x2ba01477
}

adapter driver jlink
adapter speed 12000
transport select swd

# DAPにアクセスするための1つのSWDタップを宣言
swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
# DAPを作成
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
set _TARGETNAME $_CHIPNAME.lcore
# 6つの主要なアプリケーションコアを宣言
set _smp_command ""

set $_TARGETNAME.base(0) 0x81004000
set $_TARGETNAME.base(1) 0x81005000
set $_TARGETNAME.base(2) 0x81006000
set $_TARGETNAME.base(3) 0x81007000
set $_TARGETNAME.cti(0) 0x81014000
set $_TARGETNAME.cti(1) 0x81015000
set $_TARGETNAME.cti(2) 0x81016000
set $_TARGETNAME.cti(3) 0x81017000


set _cores 4
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {

    set _TARGETNAME $_CHIPNAME.lcore

    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0

    target create \${_TARGETNAME}$_core aarch64 -dap $_CHIPNAME.dap -coreid  $_core -cti cti\$_core -dbgbase [set $_TARGETNAME.base($_core)]

    if { $_core != 0 } {
        ${_TARGETNAME}$_core configure -defer-examine
    } else {
        # ハードウェアスレッド擬似RTOSを使用するにはコメントを外す
        # ${_TARGETNAME}$_core configure -rtos hwthread"
        ${_TARGETNAME}$_core configure -work-area-size 0x30000 -work-area-phys 0xff8c0000 \
                                -work-area-backup 0
    }
    set _smp_command "$_smp_command ${_TARGETNAME}$_core"
}
# 2番目のフラッシュバンクを追加。

#set QUADSPI 1
#set _FLASHNAME $_CHIPNAME.flash1
#flash bank $_FLASHNAME stmqspi 0 0x4000000 2 2 ${_TARGETNAME}0
#flash bank $_FLASHNAME fespi 0 0 0 0 ${_TARGETNAME}0 0xfe610000

target smp $_smp_command
targets rk3568.lcore0

デバッグアドレスはまずset $_TARGETNAME.base(0) 0x81004000で変数を初期化し、その後target create ${_TARGETNAME}$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core -dbgbase [set $_TARGETNAME.base($_core)]コマンドでそのアドレスを使用します。
cti アドレスはまずset $_TARGETNAME.cti(0) 0x81014000で変数を初期化し、その後cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0で cti を作成し、最後にtarget create ${_TARGETNAME}$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core -dbgbase [set $_TARGETNAME.base($_core)]で cti を使用し、デバッグと同時に渡します。

設定ファイル解析#

cti create#

まずcti createコマンドの解析プロセスを openocd ソースコードで分析します。

[!openocd/src/target/arm_cti.c]

static const struct command_registration cti_subcommand_handlers[] = {
    {
        .name = "create",
        .mode = COMMAND_ANY,
        .jim_handler = jim_cti_create,
        .usage = "name '-chain-position' name [options ...]",
        .help = "Creates a new CTI object",
    },
    {
        .name = "names",
        .mode = COMMAND_ANY,
        .handler = cti_handle_names,
        .usage = "",
        .help = "Lists all registered CTI objects by name",
    },
    COMMAND_REGISTRATION_DONE
};

static const struct command_registration cti_command_handlers[] = {
    {
        .name = "cti",
        .mode = COMMAND_CONFIG,
        .help = "CTI commands",
        .chain = cti_subcommand_handlers,
        .usage = "",
    },
    COMMAND_REGISTRATION_DONE
};
int cti_register_commands(struct command_context *cmd_ctx)
{
    return register_commands(cmd_ctx, NULL, cti_command_handlers);
}

command_registration構造体は設定ファイルで使用される jim コマンドの実際の関数呼び出しを定義しています。上記から呼び出される関数はjim_cti_createです：

static int jim_cti_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
	struct jim_getopt_info goi;
	jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
	if (goi.argc < 2) {
		Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv,
			"<name> [<cti_options> ...]");
		return JIM_ERR;
	}
	return cti_create(&goi);
}

static int cti_create(struct jim_getopt_info *goi)
{
	......
	static struct arm_cti *cti;
	......
	/* Create it */
	cti = calloc(1, sizeof(*cti));
	if (!cti)
		return JIM_ERR;
	/* Init cti */
	......

	/* add to list */
	list_add_tail(&cti->lh, &all_cti);

	......
	
	return JIM_OK;
}

要するに、上記のコードを実行すると、メモリを確保し、struct arm_cti *ctiポインタを初期化し、双方向リストに追加しますlist_add_tail(&cti->lh, &all_cti);これで設定ファイルから構造体リストに変換されました。

target create#

次にcti createコマンドの解析プロセスを openocd ソースコードで分析します。

[!openocd/src/target/target.c]

static const struct command_registration target_command_handlers[] = {
    ......
    {
        .name = "target",
        .mode = COMMAND_CONFIG,
        .help = "configure target",
        .chain = target_subcommand_handlers,
        .usage = "",
    },
    COMMAND_REGISTRATION_DONE
};
static const struct command_registration target_subcommand_handlers[] = {
    ......
    {
        .name = "create",
        .mode = COMMAND_CONFIG,
        .jim_handler = jim_target_create,
        .usage = "name type '-chain-position' name [options ...]",
        .help = "Creates and selects a new target",
    },
    ......
    COMMAND_REGISTRATION_DONE
};
static int jim_target_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
    struct jim_getopt_info goi;
    jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
    if (goi.argc < 3) {
        return JIM_ERR;
    }
    return target_create(&goi);
}
static int target_create(struct jim_getopt_info *goi)
{
    Jim_Obj *new_cmd;
    Jim_Cmd *cmd;
    const char *cp;
    int e;
    int x;
    struct target *target;
    struct command_context *cmd_ctx;

    ......
    /* Create it */
    target = calloc(1, sizeof(struct target));
    if (!target) {
        LOG_ERROR("Out of memory");
        return JIM_ERR;
    }

    ......
    /* Do the rest as "configure" options */
    goi->isconfigure = 1;
    e = target_configure(goi, target);

    ......
    /* append to end of list */
    append_to_list_all_targets(target);

    cmd_ctx->current_target = target;
    return JIM_OK;
}
static int target_configure(struct jim_getopt_info *goi, struct target *target)
{
	struct jim_nvp *n;
	Jim_Obj *o;
	jim_wide w;
	int e;
	/* parse config or cget options ... */
	while (goi->argc > 0) {
			if (target->type->target_jim_configure) {
			/* target defines a configure function */
			/* target gets first dibs on parameters */
			e = (*(target->type->target_jim_configure))(target, goi);
			if (e == JIM_OK) {
				/* more? */
				continue;
			}
			if (e == JIM_ERR) {
				/* An error */
				return e;
			}
			/* otherwise we 'continue' below */
		}
		......
		switch (n->value) {
		case TCFG_TYPE:
			......
		case TCFG_EVENT:
			......

		case TCFG_WORK_AREA_VIRT:
			......
		case TCFG_WORK_AREA_PHYS:
			......
		case TCFG_WORK_AREA_SIZE:
			......
		case TCFG_WORK_AREA_BACKUP:
			......
		case TCFG_ENDIAN:
			......
		case TCFG_COREID:
			......
		case TCFG_CHAIN_POSITION:
			......
		case TCFG_DBGBASE:
			if (goi->isconfigure) {
				e = jim_getopt_wide(goi, &w);
				if (e != JIM_OK)
					return e;
				target->dbgbase = (uint32_t)w;
				target->dbgbase_set = true;
			} else {
				if (goi->argc != 0)
					goto no_params;
			}
			Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->dbgbase));
			/* loop for more */
			break;
		case TCFG_RTOS:
			......

		case TCFG_DEFER_EXAMINE:
			......
		case TCFG_GDB_PORT:
			......
		case TCFG_GDB_MAX_CONNECTIONS:
			......
		}
	} /* while (goi->argc) */
		/* done - we return */
	return JIM_OK;
}

上記のコードから、デバッグアドレスは最終的にtarget->dbgbaseに保存され、ターゲットは最終的にappend_to_list_all_targets(target);でall_targetの単方向リストに追加されます。

しかし、上記のコードには cti アドレスの解析部分がなく、オプション部分でも確かにありません。

static struct jim_nvp nvp_config_opts[] = {
	{ .name = "-type",             .value = TCFG_TYPE },
	{ .name = "-event",            .value = TCFG_EVENT },
	{ .name = "-work-area-virt",   .value = TCFG_WORK_AREA_VIRT },
	{ .name = "-work-area-phys",   .value = TCFG_WORK_AREA_PHYS },
	{ .name = "-work-area-size",   .value = TCFG_WORK_AREA_SIZE },
	{ .name = "-work-area-backup", .value = TCFG_WORK_AREA_BACKUP },
	{ .name = "-endian",           .value = TCFG_ENDIAN },
	{ .name = "-coreid",           .value = TCFG_COREID },
	{ .name = "-chain-position",   .value = TCFG_CHAIN_POSITION },
	{ .name = "-dbgbase",          .value = TCFG_DBGBASE },
	{ .name = "-rtos",             .value = TCFG_RTOS },
	{ .name = "-defer-examine",    .value = TCFG_DEFER_EXAMINE },
	{ .name = "-gdb-port",         .value = TCFG_GDB_PORT },
	{ .name = "-gdb-max-connections",   .value = TCFG_GDB_MAX_CONNECTIONS },
	{ .name = NULL, .value = -1 }
};

上記の設定をグローバル検索して "-cti" を見つけると、以下のコードが見つかります：

[!openocd/src/target/aarch64.c]

static const struct jim_nvp nvp_config_opts[] = {
    { .name = "-cti", .value = CFG_CTI },
    { .name = NULL, .value = -1 }
};
static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi)
{
	struct aarch64_private_config *pc;
	struct jim_nvp *n;
	int e;

	pc = (struct aarch64_private_config *)target->private_config;
	......
	/*
	 * Call adiv5_jim_configure() to parse the common DAP options
	 * It will return JIM_CONTINUE if it didn't find any known
	 * options, JIM_OK if it correctly parsed the topmost option
	 * and JIM_ERR if an error occurred during parameter evaluation.
	 * For JIM_CONTINUE, we check our own params.
	 */
	e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
	if (e != JIM_CONTINUE)
		return e;

	/* parse config or cget options ... */
	if (goi->argc > 0) {
		......

		switch (n->value) {
		case CFG_CTI: {
			if (goi->isconfigure) {
				Jim_Obj *o_cti;
				struct arm_cti *cti;
				e = jim_getopt_obj(goi, &o_cti);
				if (e != JIM_OK)
					return e;
				cti = cti_instance_by_jim_obj(goi->interp, o_cti);
				if (!cti) {
					Jim_SetResultString(goi->interp, "CTI name invalid!", -1);
					return JIM_ERR;
				}
				pc->cti = cti;
			} else {
				if (goi->argc != 0) {
					Jim_WrongNumArgs(goi->interp,
							goi->argc, goi->argv,
							"NO PARAMS");
					return JIM_ERR;
				}

				if (!pc || !pc->cti) {
					Jim_SetResultString(goi->interp, "CTI not configured", -1);
					return JIM_ERR;
				}
				Jim_SetResultString(goi->interp, arm_cti_name(pc->cti), -1);
			}
			break;
		}

		default:
			return JIM_CONTINUE;
		}
	}

	return JIM_OK;
}

これにより、cti はターゲットの位置target->private_config->ctiに保存されることがわかります。
この関数はどこで呼び出されるのでしょうか？それは関数ポインタを介して呼び出され、呼び出しの場所は以前のtarget_configure関数内です。

struct target_type armv8r_target = {
	......
	.target_jim_configure = aarch64_jim_configure,
	......
};

static int target_configure(struct jim_getopt_info *goi, struct target *target)
> {
	struct jim_nvp *n;
	Jim_Obj *o;
	jim_wide w;
	int e;

	/* parse config or cget options ... */
	while (goi->argc > 0) {
		Jim_SetEmptyResult(goi->interp);
		/* jim_getopt_debug(goi); */

		if (target->type->target_jim_configure) {
			/* target defines a configure function */
			/* target gets first dibs on parameters */
			e = (*(target->type->target_jim_configure))(target, goi);
			if (e == JIM_OK) {
				/* more? */
				continue;
			}
			if (e == JIM_ERR) {
				/* An error */
				return e;
			}
			/* otherwise we 'continue' below */
		}
		......

これで、2 つの設定ファイルのアドレスがコード内の指定された位置に保存されました。最終的に、デバッグアドレスはall_targets->dbgbaseに、cti アドレスはall_targets->private_config->cti->spot.baseに保存されます。

検証#

target_create関数の最後に印刷情報を追加し、上記の保存位置に従って印刷します：

	if(target->private_config != 0 && target->dbgbase != 0)
	{
		struct aarch64_private_config *pc = (struct aarch64_private_config *)target->private_config;

		LOG_DEBUG("[debug] debug address : 0x%X\n",target->dbgbase);
		LOG_DEBUG("[debug] cti   address : 0x%X\n",pc->cti->spot.base);
	}

	/* append to end of list */
	append_to_list_all_targets(target);

テスト出力は、設定ファイルのパラメータと同じです：

Debug: 43 1 target.c:5934 target_create(): [debug] debug address : 0x81004000
Debug: 44 1 target.c:5935 target_create(): [debug] cti   address : 0x81014000
Debug: 74 1 target.c:5934 target_create(): [debug] debug address : 0x81005000
Debug: 75 1 target.c:5935 target_create(): [debug] cti   address : 0x81015000
Debug: 102 2 target.c:5934 target_create(): [debug] debug address : 0x81006000
Debug: 103 2 target.c:5935 target_create(): [debug] cti   address : 0x81016000
Debug: 130 2 target.c:5934 target_create(): [debug] debug address : 0x81007000
Debug: 131 2 target.c:5935 target_create(): [debug] cti   address : 0x81017000

デバッグアドレスと cti アドレスとは何か#

openocd ソースコードでは、dbgbase と共に使用される一連のマクロがあり、使用方法はデバッグ基準アドレス + オフセットアドレスの方式でいくつかのレジスタにアクセスします：

/* register offsets from armv8.debug_base */
#define CPUV8_DBG_MAINID0		0xD00
#define CPUV8_DBG_CPUFEATURE0	0xD20
#define CPUV8_DBG_DBGFEATURE0	0xD28
#define CPUV8_DBG_MEMFEATURE0	0xD38

#define CPUV8_DBG_LOCKACCESS 0xFB0
#define CPUV8_DBG_LOCKSTATUS 0xFB4

#define CPUV8_DBG_EDESR		0x20
#define CPUV8_DBG_EDECR		0x24
#define CPUV8_DBG_EDWAR0	0x30
#define CPUV8_DBG_EDWAR1	0x34
#define CPUV8_DBG_DSCR		0x088
#define CPUV8_DBG_DRCR		0x090
#define CPUV8_DBG_ECCR		0x098
#define CPUV8_DBG_PRCR		0x310
#define CPUV8_DBG_PRSR		0x314

#define CPUV8_DBG_DTRRX		0x080
#define CPUV8_DBG_ITR		0x084
#define CPUV8_DBG_SCR		0x088
#define CPUV8_DBG_DTRTX		0x08c

#define CPUV8_DBG_BVR_BASE	0x400
#define CPUV8_DBG_BCR_BASE	0x408
#define CPUV8_DBG_WVR_BASE	0x800
#define CPUV8_DBG_WCR_BASE	0x808
#define CPUV8_DBG_VCR		0x01C

#define CPUV8_DBG_OSLAR		0x300

#define CPUV8_DBG_AUTHSTATUS	0xFB8

cti に関連するものも同様です：

/*define CTI(cross trigger interface)*/
#define CTI_CTR				0x0
#define CTI_INACK			0x10
#define CTI_APPSET			0x14
#define CTI_APPCLEAR		0x18
#define CTI_APPPULSE		0x1C
#define CTI_INEN0			0x20
#define CTI_INEN1			0x24
#define CTI_INEN2			0x28
#define CTI_INEN3			0x2C
#define CTI_INEN4			0x30
#define CTI_INEN5			0x34
#define CTI_INEN6			0x38
#define CTI_INEN7			0x3C
#define CTI_INEN8			0x40
#define CTI_INEN(n)			(0x20 + 4 * n)
#define CTI_OUTEN0			0xA0
#define CTI_OUTEN1			0xA4
#define CTI_OUTEN2			0xA8
#define CTI_OUTEN3			0xAC
#define CTI_OUTEN4			0xB0
#define CTI_OUTEN5			0xB4
#define CTI_OUTEN6			0xB8
#define CTI_OUTEN7			0xBC
#define CTI_OUTEN8			0xC0
#define CTI_OUTEN(n)		(0xA0 + 4 * n)
#define CTI_TRIN_STATUS		0x130
#define CTI_TROUT_STATUS	0x134
#define CTI_CHIN_STATUS		0x138
#define CTI_CHOU_STATUS		0x13C
#define CTI_GATE			0x140
#define CTI_UNLOCK			0xFB0

上記のマクロの名前と値に基づいて、Arm Architecture Reference Manual for A-profile architectureを参照すると、H8 および H9 章がこの部分のレジスタに関する説明を行っています：
Pasted image 20240508175124Pasted image 20240508145329
全体の H 章は 外部デバッグ (External Debug) の機能について説明しています：

Part H: External Debug
H1: About External Debug
H2: Debug State
H3: Halting Debug Events
H4: The Debug Communication Channel and Instruction Transfer Register
H5: The Embedded Cross-Trigger Interface
H6: Debug Reset and Powerdown Support
H7: The PC Sample-based Profiling Extension
H8: About the External Debug Registers
H8.1 Relationship between external debug and System registers
H8.2 Endianness and supported access sizes
H8.3 Synchronization of changes to the external debug registers
H8.4 Memory-mapped accesses to the external debug interface
H8.5 External debug interface register access permissions
HB.6 External debug interface registers
HB.7 Cross-trigger interface registers
H8.8 External debug register resets
H9: External Debug Register Descriptions
H9.1 About the external debug registers
H9.2 External debug registers
H9.3 External trace registers
H9.4 External Trace Buffer registers
H9.5 Cross-Trigger Interface registers

その他の参考資料：【芯片 DFX】万子長文和你一起探索 Arm 调试架构 - 极术社区 - 连接开发者与智能计算生态 (aijishu.com)

アドレスの出所#

まず、以下のような初歩的な設定ファイルを作成します。dap を作成するだけです：

[!/usr/local/share/openocd/scripts/target/rk3568.cfg]

# SPDX-License-Identifier: GPL-2.0-or-later
reset_config trst_and_srst separate
if { [info exists CHIPNAME] } {
  set _CHIPNAME $CHIPNAME
} else {
  set _CHIPNAME rk3568
}

#
# Main DAP
#
if { [info exists DAP_TAPID] } {
   set _DAP_TAPID $DAP_TAPID
} else {
   set _DAP_TAPID 0x2ba01477
}

adapter driver jlink
adapter speed 12000
transport select swd

# DAPにアクセスするための1つのSWDタップを宣言
swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
# DAPを作成
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0

次に openocd を起動し、telnet コマンドインターフェースに入り、rk3568.dap info を入力して ROM_Table を取得します：

openocd -f interface/jlink.cfg -f target/rk3568.cfg

telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> rk3568.dap info
AP # 0x0
                AP ID register 0x24770002
                Type is MEM-AP APB2 or APB3
MEM-AP BASE 0x80000003
                Valid ROM table present
                Component base address 0x80000000
                Peripheral ID 0x0000080000
                Designer is 0x000, <invalid>
                Part is 0x000, Unrecognized
                Component class is 0x1, ROM table
                MEMTYPE system memory not present: dedicated debug bus
        ROMTABLE[0x0] = 0x01000003
                Component base address 0x81000000
                Peripheral ID 0x04007bb4e3
                Designer is 0x23b, ARM Ltd
                Part is 0x4e3, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x00, Miscellaneous, other
                Dev Arch is 0x47700af7, ARM Ltd "CoreSight ROM architecture" rev.0
                Type is ROM table
                MEMTYPE system memory not present: dedicated debug bus
        [L01] ROMTABLE[0x0] = 0x00001006
                Component not present
        [L01] ROMTABLE[0x4] = 0x00002006
                Component not present
        [L01] ROMTABLE[0x8] = 0x00004003
                Component base address 0x81004000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0xc] = 0x00005003
                Component base address 0x81005000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x10] = 0x00006003
                Component base address 0x81006000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x14] = 0x00007003
                Component base address 0x81007000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x15, Debug Logic, Processor
                Dev Arch is 0x47708a15, ARM Ltd "Processor debug architecture (v8.2-A)" rev.0
        [L01] ROMTABLE[0x18] = 0x00008002
                Component not present
        [L01] ROMTABLE[0x1c] = 0x00009002
                Component not present
        [L01] ROMTABLE[0x20] = 0x0000a002
                Component not present
        [L01] ROMTABLE[0x24] = 0x0000b002
                Component not present
        [L01] ROMTABLE[0x28] = 0x0000c003
                Component base address 0x8100c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x2c] = 0x0000d003
                Component base address 0x8100d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x30] = 0x0000e003
                Component base address 0x8100e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x34] = 0x0000f003
                Component base address 0x8100f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x16, Performance Monitor, Processor
                Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
        [L01] ROMTABLE[0x38] = 0x00014003
                Component base address 0x81014000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x3c] = 0x00015003
                Component base address 0x81015000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x40] = 0x00016003
                Component base address 0x81016000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x44] = 0x00017003
                Component base address 0x81017000
                Peripheral ID 0x04007bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x14, Debug Control, Trigger Matrix
                Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
        [L01] ROMTABLE[0x48] = 0x0001c003
                Component base address 0x8101c000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x4c] = 0x0001d003
                Component base address 0x8101d000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x50] = 0x0001e003
                Component base address 0x8101e000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x54] = 0x0001f003
                Component base address 0x8101f000
                Peripheral ID 0x04003bbd05
                Designer is 0x23b, ARM Ltd
                Part is 0xd05, Unrecognized
                Component class is 0x9, CoreSight component
                Type is 0x13, Trace Source, Processor
                Dev Arch is 0x47724a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.2
        [L01] ROMTABLE[0x58] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x5c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x60] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x64] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x68] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x6c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x70] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x74] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x78] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x7c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x80] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x84] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x88] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x8c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x90] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x94] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x98] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x9c] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xa8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xac] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xb8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xbc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xc8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xcc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xd8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xdc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xe8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xec] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf0] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf4] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xf8] = 0x00000002
                Component not present
        [L01] ROMTABLE[0xfc] = 0x00000002
                Component not present
        [L01] ROMTABLE[0x100] = 0x00000002
                Component not present
        ROMTABLE[0x4] = 0x00000000
                End of ROM table
>

ここで **ARM Ltd "Processor debug architecture (v8.2-A)"** に対応する 4 つのオプションがデバッグアドレスに、ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0に対応する 4 つのオプションが cti アドレスに対応しています。

読み込み中...
文章は、創作者によって署名され、ブロックチェーンに安全に保存されています。